1. Field of the Invention
This invention relates to semiconductor devices of different types that closely spaced and are connected by conductive connectors. More specifically, the present invention relates to different complementary metal-oxide-semiconductor (CMOS) devices that are adjacent to each other, such as n-channel field effect transistors (n-FETs) and p-channel field effect transistors (p-FETs), which connected by conductive connectors that include different dopants associated with the different CMOS devices.
2. Description of Related Art
As semiconductor devices scale, spacing between the CMOS devices become smaller. Devices of different types, such as field effect transistors (FETs) having different performance characteristics, may be placed adjacent to each other, and share certain physical components. For example, in devices such as a static random access memory (SRAM), adjacent pFET and nFET devices may share a common gate conductor, which at the pFET includes a different dopant than at the nFET.
However, as the spacing between devices decreases, dopants of different types may diffuse along a shared gate conductor to such an extent that it encroaches on and changes the properties of the adjacent device having a different dopant. Such cross diffusion may adversely alter properties such as the threshold voltage of a transistor. The undesired variation of device property results in poor product performance and yield.
For example, FIG. 1 illustrates an nFET device 20 adjacent to a pFET device 30, having channel regions 21, 31 formed in a semiconductor substrate 4. The nFET 20 is electrically isolated from the pFET 30 by isolation regions 25. Gate dielectric layers 24 are formed atop the channel region of the nFET 21 and the channel region of the pFET 31. Overlaying both the nFET channel 21 and pFET channel 31 atop the gate dielectric 24 is a gate conductor 10, which includes an N+ doped region 10′ over the nFET channel 21 and a P+ doped region 10″ over the pFET channel 31. A spacer 12 is formed on the sidewalls of the gate conductor 10. However, the N+ and P+ dopants may cross diffuse in the gate conductor region 10″′ between the nFET and pFET due to effects such as implant mask overlay errors and thermal anneal. If the cross-diffusion region 10″′ encroaches over the channel regions of the nFET or pFEt, there may be changes in work function. To avoid this problem, the spacing 14 between the nFET and pFET must be maintained sufficiently large so that the cross-diffusion region 10″′ encroachment over the device channel will be minimized, which limits scaling of chip density.
Referring to FIG. 2, the Vt for a pFET, which is adjacent an nFET in an SRAM, is plotted on the vertical axis as a function of gate length Lpoly between the pFET and the nFET. The lower grouping of data points (line 33) represents widely spaced devices. The dark filled circles represent data points without additional thermal anneal while the filled triangles represent data points with additional thermal budget. Since the nFET and pFET are sufficiently spaced apart, there would be no Vt shift. However, if the nFET and pFET are sufficiently close together (open circles 35 and triangles 37), the additional thermal budget (open triangles 37) exhibit a significant shift in Vt due to cross diffusion relative to the pFETs prior to the anneal (open circles 35).
In view of the above, it would be desirable to form a gate conductor structure with reduced dopant cross diffusion without impacting density of the circuit layout and allow scaling of closely spaced devices.